1. Field of the Invention
This invention relates generally to CMOS voltage multiplier circuits and more particularly, it relates to an improved CMOS voltage multiplier for use in mixed signal circuits which includes means for sensing the highest potential node of an N-well process and for automatically connecting the local substrate thereof to the highest potential so as to avoid turning on the substrate.
2. Description of the Prior Art
As is generally well-known in the IC industry, there has been a trend of manufacturing semiconductor integrated circuit chips with a very high density so as to contain a larger and larger number of circuit components, such as VLSI chips. As a result, the problem of high power consumption for these integrated circuit chips has become a major concern. One of the ways in which the semiconductor IC manufacturers have used to solve this problem is to reduce the power supply voltage VCC (e.g., from +5.0 volts to +3.0 volts or lower). Nowadays, some of the integrated circuit chips fabricated in standard CMOS process technology have been designed to operate at a supply potential of +2.5 V or even below.
However, modern integrated circuit chips operable with a low power supply voltage are typically required to interface with previously developed CMOS semiconductor technologies operable with a higher power supply voltage. Further, in mixed signal circuits such as in a computer system some of the integrated circuit chips can function with only a low power supply voltage, but other integrated circuit chips require the higher power supply voltage. As used herein, the term "mixed signal circuits" refers to any circuit which contains both digital circuitry and analog circuitry. Therefore, while the newer digital circuitry may still be operable with the lower power supply voltage, there is imposed severe design limitations on the analog circuitry.
In order to overcome this drawback, there has been developed in the prior art of on-chip high-voltage generation circuitry which are capable of producing a relatively higher power supply voltage by multiplying a relatively low power supply voltage so as to provide more head room for the analog circuitry. One such method is illustrated in FIG. 1 and is labeled as "Prior Art," wherein a voltage multiplier circuit 2 is utilized in a VLSI mixed signal circuit 4 having digital circuitry 6 and analog circuitry 8. While the off-chip power supply voltage V.sub.PS is adequate to operate the digital circuitry 6, it is too low for driving the analog circuitry 8. Thus, the voltage multiplier circuit 2 serves to multiply the external power supply voltage V.sub.PS by n so as to provide a higher on-chip voltage nV.sub.PS for operating the analog circuitry 8. A multiplexer 7 has its inputs connected to the digital circuitry 6 for receiving a plurality of clocking signals CLK1, CLK2, . . . CLKn each being of a different frequency and generating selectively on its output one of the clocking signals defining a selected clock signal CLK. The selected clock signal CLK is used to regulate the charging rate of the voltage multiplier 2.
However, this use of the voltage multiplier 2 for generating a higher power supply voltage nV.sub.PS is not without any problems. In the past, the voltage multiplier 2 is formed of a plurality of CMOS transistors each being formed of either a PMOS or NMOS transistor connected in series between an input terminal and output terminal. Each of the PMOS or NMOS transistors is fabricated conventionally in a CMOS technology and includes a gate, source, drain, and a bulk region (N-well for P-channel devices). For the P-channel devices, the bulk region or local substrate is generally tied to the external power supply voltage V.sub.PS. Further, the drain region of the PMOS transistor in the last stage is tied to the output terminal. Therefore, when the output voltage exceeds the external power supply voltage the p-n junction of the drain-substrate becomes forward biased or turned ON where unnecessarily wasted power occurs, thereby reducing the efficiency of the voltage multiplier.
It would therefore be desirable to provide an improved voltage multiplier for use in a mixed signal circuit which achieves power savings and thus enhanced performance. The high-voltage generation circuit of the present invention includes a voltage comparator circuit for comparing the external power supply voltage and the output voltage and for generating a control logic signal. Switching circuity is responsive to the control logic signal for automatically connecting the local substrate of the transistors in the voltage multiplier stages to one of the external power supply voltages and the output voltage so as to avoid turning on of the local substrate.